LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY x IS
PORT(
  a,b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  c:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END x;
ARCHITECTURE play OF x IS
SIGNAL indata:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
  indata<=a&b;
  PROCESS(indata)
    BEGIN
    CASE indata IS
       WHEN "00000000"=>c<="0000";
       WHEN "00010001"=>c<="0001";
       WHEN "00100010"=>c<="0010";
       WHEN "00110011"=>c<="0011";
       WHEN "01000100"=>c<="0100";
       WHEN "01010101"=>c<="0101";
       WHEN "01100110"=>c<="0110";
       WHEN "01110111"=>c<="0111";
       WHEN "10001000"=>c<="1000";
       WHEN "10011001"=>c<="1001";
       WHEN OTHERS=>c<="1111";
    END CASE;
  END PROCESS;
END play;    